Product Development Student Worker

Product Development Student Worker
Empresa:

Intel


Product Development Student Worker

Detalles de la oferta

The Manufacturing validation group in Costa Rica is looking for motivated student worker to join the team and work in the highly challenging environment of product development across Intel's product families. The product development engineers in this team work in Architecture definitions, Circuit and Logic Design and Development recommendation for implementations, Verification and Validation model development, Functional and Structural functional test content development with teams worldwide. The team is responsible to maintain Intel's design and manufacturing quality of baseline product to the external world. This engineering team is specifically responsible for ensuring the testability and manufacturability of the Analog content from architectural design through to production ramp.

Qualifications

Minimum Qualifications
You should be a student in the Electrical/Electronic Engineering (more than 70% completed) or equivalent career or a MS degree student in Electrical/Electronic Engineering or equivalent career
Experience in the following areas will be a plus:
- Hardware architecture, logic/Circuit design and implementation
- Experience in programming languages: perl, python, C++, etc
- Experience in DFT, hardware testing methods and tools
- Experience in high speed circuit testing (oscilloscope and JBERT usage, etc)

Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

CRInternJR0121476San Jose

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