Do Something WonderfulIntel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below.- Life at Intel- Diversity at IntelIntel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.Our design team is part of the NXNE (Xeon and Networking Engineering) group that delivers next generation edge and networking products. We are a small, tightly knit group of analog circuit, logic, and layout designers located primarily in Allentown, Pennsylvania who are dedicated to helping Intel achieve its goals by enabling world-class foundational and custom IP development and test chips, end-to-end circuit design, and power, performance, area analysis.We are looking for the right person to take an IP Design Kit Engineer position to create and support timing, physical, and functional modeling view for the foundational analog IP designed within our team. We want someone to collect and deploy all required IP for our internal and external customers.The key responsibilities of this person include the following:Create timing, physical, and functional modeling views for analog and mixed signal designs.Work closely with design and layout engineers to understand IP complexity and create robust model views that enable construction and PV sign-off flows.Verify the quality and integrity of various model views.Assemble complete collateral package and deploy to both internal and external customers.Support SOC teams in their standard cell library and memory selection and usage and interface to the corporate teams for any issues or enhancements.Interface to SOC teams to provide IP support and track down answers to any issues.The IP Design Kit Engineer should possess the following attributes:- Excellent communication: Expected to drive clarity across partners and customers.- Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can.**Qualifications**:What we need to see (Minimum Qualifications):- Bachelor's degree in Electrical Engineering, Computer Engineering or related technical field with 5+ years' experience OR a Masters degree in in Electrical Engineering, Computer Engineering or related technical field and 3+ years of related experience- 4+ years of experience in IP development or SOC design- 4+ years of experience in Spice level simulation- 4+ years of experience working with Synopsys timing and physical models and Verilog functional models.- Understanding of SOC design methodologies and verification.- Intermediate to advanced English & communication skills.How to stand out (Preferred Qualifications):- Experience with Synopsys Liberty modeling format, including NLDM, CCS, OCV.- Experience with PrimeTime, Fusion Compiler, or Static Timing Analysis including constraints (.sdc) and ETM.- Experience with Verilog/RTL language and simulators.- Experience with characterization tools (SiliconSmart, Liberate) and characterization methodologies.- Familiarity with Synopsys NDM and Milkyway physical modeling views- Familiarity with Cadence Virtuoso for schematic viewing- Understanding of memories and memory compilers- 1+ years' experience with scripting language like Perl, TCL, Python, etc.- Experience with synthesis and understanding of standard cell offerings.**Inside this Business Group**:Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.**Posting Statement**:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.**Benefits**:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.**Working Model**:This role will be eligible for our hybrid w
